Skip to main content

Intel India is hiring Senior Design Automation Engineer - IO Family Build Automation - 710314


Description

This position is in IDGz HIP Design automation team (HIP DA). HIP DA provides design automation tools, flows and methods for designing world class HIP such as PCIe, DDR, SATA, LDOs, ..etc. In this role, you will develop and support world class design automation for automated layout and EDA views generation for IO families such as CFIOs, LDO family or Serial IOs.

Qualifications

B.S./M.S. in EE/CS

3+ years design automation experience in developing physical design flow using SNPS-ICC/Magma-Blast Fusion or Intel Internal tools such as Genesys needed

Solid understanding of design rules, floorplanning, power grid planning, Clock tree routing, automated routing methodologies needed

Solid automation skills in PERL/TCL required

Understanding of reliability issues such as EM/IR/ESD are highly desirable

Flexibility of working in different physical design tools is a MUST - ICC/Genesys

Candidate must have strong communication skills and strong motivation for customer support

Ability to multi-task and flexibility to work in global environment needed.

Job Category: Engineering
Primary Location: India-India, Bangalore
Full/Part Time: Full Time
Job Type: Experienced
Regular/Temporary: Regular
Posting Date: Apr 25, 2013
Apply Before: Jul 1, 2013
Labels:

Comments

Post a Comment

Popular posts from this blog

Walk in Interview for Vehicle Upholstery Fitters at Saud Bahwan Group {Muscat-Oman}

Company Name: Saud Bahwan Grou Job Description: Automobile Service - Passenger Cars/ Heavy Commercial Vehicles {To carry out the seat upholstery related jobs in passenger cars/ buses, including making/ repairing/ replacing.} Qualification: 10th Pass/ ITI (preferably in Motor mechanic trade) from State Board of Examination/ national Council for Vocational Training (NCVT). Experience: 3-8 years relevant experience with reputed automobile dealers' workshops or authorized service centers. Job Location: Muscat - Oman Date of Walk in Interview: February 25 th 2013 Timings: between 09:00 AM to 02:00 PM Salary: An attractive tax-free salary with high savings potential, bachelor sharing accommodation, subsidized mess facilities, free transportation, annual air passage, 30 days annual leave, gratuity, free medical care, incentives etc., will be offered to the selected candidates. Candidates meeting the above requirements and willing to join us immediately may
Post a Comment
Read more

Intel Technology is hiring SOC Timing Lead

Company Name: Intel Technology India Private Limited Job Description: SOC Timing Lead Job Reference: 725979 Work Experience: 10 – 12 Years Work Location: Bangalore Education: UG - B. Tech/B.E, PG - M. Tech Doctorate - Any Doctorate - Any Specialization, Doctorate Not Required Job Segments: Engineer, Electrical, Electronics Engineer, Engineering Job Description Component Design Engineers are responsible for the design and development of electronic components. Responsibilities may include: the design of chip layout circuit design, circuit checking, device evaluation and characterization, documentation of specifications, prototype construction and checkout, modification and evaluation of semiconductor devices and components, performing developmental and/or test work, reviewing product requirements and logic diagrams, planning and organizing design projects or phases of design projects. Responds to customer/client requests or events as they occur. Develops
Read more

Sankalp Semiconductor is hiring for Digital Verification Engineer

Entity Name: Sankalp Semiconductor Private Limited Job Name: Digital Verification Engineer Work Experience: 4 to 8 years Work Location: Bengaluru,  Ahmadabad Educational Qualification: BE or B. Tech Job Description. Digital Verification team is working on IP verification and SoC verification projects for our various tier 1 & tier2 global customers. This team provides verification solution for the entire verification cycle using industry standard methodology & tool. Candidate should be able to perform IP/SoC functional simulation, gate level simulation/low power simulation independently at Sankalp/Customer work location. Roles and Responsibilities Work on SoC/Sub-system/IP verification projects for our customers Lead team of junior and mid-level engineers Customer interfacing for technical requirements Defining and developing project execution plan as per requirements Define verification metrics and tracking for verification sign-off Handl
Read more