Company Name:
Intel Technology India Private Limited
Job Description:
Soc FE Design and Verification
Job Reference: 712111
Working Experience:
8-9 Years
Work Location:
Bengaluru
Apply Before: June
30th 2013
Qualifications
Candidate must
have a Master of Science degree in Electrical Engineering or equivalent from
recognized university with at -least 5 years’ experience in VLSI chip design
and verification.
Proven
microarchitecture design and implementation experience
Knowledge of
Power management tools/flows
In-depth
experience with coding in HDL languages such as System Verilog
Detailed
hands-on experience with RTL Verification design flows (OVM, UVM), HDL
languages (Verilog and/or System Verilog), and other industry standard EDA
tools/flows
Proficient in
digital logic design, state machine (FSM) design, RTL verification and debug.
Expertise in ASIC/FPGA design flows is highly desired
Good knowledge
of computer system architecture is preferred
Expertise in TCL
Perl language is a plus
Expertise in DFT
is a plus
The ideal
candidate would be disciplined, motivated and innovative, with a focus on
quality. The candidate must be a team player and be flexible and open to a
variety of task assignments in the design team and work effectively in a multi
geo team
Job Description:
In
this position, you will be an integral part of Intel Labs' team in Bangalore
whose charter is to innovate, build and demonstrate cutting edge SOC
technologies via silicon prototyping. You will be responsible for design and
verification of the front-end logic for the next generation SOC silicon
prototypes.
Your
responsibilities will include but not be limited to:
Developing
the micro- architecture based on High Level Architecture Specs
Interacting
with architects, engineers/experts in other areas like circuit design,
synthesis and performance verification to ensure that logic capabilities meet
the design needs and fit into the design flow
Work
on multidisciplinary research and collaborate with design, layout and/or
hardware engineers in the design and validation of VLSI systems.
Learning
and contributing in various design and implementation tasks
System
level simulation
Gate
level simulation
